Artificial Intelligence in Semi-Conductor Chips

Authors

  • Vandana Bhat Assistant Professor, Dept. of MCA, M.P.E.Society’s S.D.M.College, Honnavar, India Author
  • Madhura Bhat Assistant Professor, Dept. of Computer Science, M.P.E.Society’s S.D.M.College, Honnavar, India Author
  • Manjunath Dixit Assistant Professor, Dept. of BCA, M.P.E.Society’s S.D.M.College, Honnavar, India Author
  • Subrahmanya Bhat Assistant Professor, Dept. of BCA, M.P.E.Society’s S.D.M.College, Honnavar, India Author
  • Shrikant Bhat Assistant Professor, Dept. of BCA, M.P.E.Society’s S.D.M.College, Honnavar, India Author
  • Nitin Bandekar PG Scholar, Dept. of MCA, M.P.E.Society’s S.D.M.College, Honnavar, India Author

DOI:

https://doi.org/10.47392/IRJAEM.2026.0127

Keywords:

AI Accelerators, Neuromorphic Computing, GAAFET, 3D IC Packaging, Edge AI, RISC-V

Abstract

By 2026, the global semiconductor scene looks pretty different, instead of everyone relying on giant GPU clusters, the industry has moved toward distributed, specialized AI accelerators. Here, we dig into how neuromorphic computing and 3D-stacked Gate-All-Around (GAAFET) transistors come together to break through the old “Power Wall” that held back AI processing. Our framework for on-chip adaptive learning cuts data center dependence by 40 percent a big shift. What stands out is this: combining RISC-V architectures with spiking neural networks (SNNs) delivers the speed you need for real-time, agentic AI.

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Published

2026-04-13